Complex electronic systems usually include multiple circuits or subcircuits. Several circuits or subcircuits may reside on one IC or on different ICs. A circuit may operate with a clock signal to synchronize signals entering and leaving the circuit. Such a circuit is known as a synchronous circuit. Circuits that do not have a clock signal for controlling signals entering and leaving the circuit are known as asynchronous circuits. Different synchronous circuits may have differing timing requirements. Problems or errors in system operations can occur when signals are transmitted between circuits that have different timing requirements. Therefore, various circuits and methods exist to synchronize signals transmitted between circuits in a system.
An example of an asynchronous circuit is a nonvolatile memory device, such as a flash memory device. An asynchronous nonvolatile memory that is a discrete integrated circuit is accessed at random by other circuits that require data stored at particular addresses of the memory device. Nonvolatile memory devices are accessed by a variety of signals, including a mutli-bit address signal. In some memory devices, it is worthwhile to detect a transition on the incoming address lines so that the memory device can be prepared for an upcoming access. In various circumstances, the ability to detect an access makes the memory device more efficient. For example, detecting a transition on an address line indicates that a memory access has begun, allowing a device can to also determine when the memory access has completed and power down word lines accordingly.
Memory devices that detect address signal transitions typically include some circuitry that produces an address transition detection (ATD) signal. The ATD signal can be used for, among other things, preparing sensing circuits. For example, nodes that are known to be slow to slew can be precharged to some equilibrium point, that is, to a voltage midway between the voltage representing logic one and the voltage representing logic zero. Preparation of sensing circuits decreases access time. An ATD signal can also be used to initiate bit line charging and word line boosting. Bit line charging and word line boosting are known in the art.
For memory devices with certain semiconductor architectures, ATD signals are particularly useful to initiate word line powerdown. As is known, in memory devices with a single-well semiconductor architecture, it is necessary to place a positive voltage of, for example, five volts on a word line at the same time as a negative voltage of five volts on the gate of a blocking transistor, such that a ten volt oxide stress results. If a ten volt oxide stress is maintained, the device will break down. It is known, however, that read operations occur only intermittently and that a single word line is only used in some read operations. It is possible, to greatly reduce the amount of time that the oxide realizes a ten volt stress by powering down the word line to zero volts when it is not being used for a read operation. An ATD signal allows this to be done because the ATD signal indicates when a read operation is completed.
Circuits currently exist for detecting address transitions in memory devices, but they posses some inadequacies that cause improper memory operations under some circumstances. FIG. 1 is a block diagram of prior art address transition detection circuitry. Address signals A0-AN enter the ATD circuitry from address pads. Integrated circuit 141 is a nonvolatile memory. Address pads 132 and 134 are shown. Address pad 132 carries an external address signal 106, which is labeled A0. Address pad 134 carries external address signal 108, which is labeled AN. A complete address may include various numbers of bits. Address signals between signal 106 and 108 are not shown in FIG. 1. Each address signal entering an integrated circuit 141 passes through an input buffer such as buffer 102. The output of buffer 102 is internal address signal 104. Internal address signal 104 is transmitted along address path 151 to be used for addressing the memory device in a conventional way. Parallel to address path 151 is an address transition detection path that begins with internal address 104, which is an input to XOR gate 118. Internal address signal 104 is also an input to delay circuit 114. XOR gate 118 compares internal address signal 104 with the delayed version of itself (signal 116) and outputs an active address transition detection (ATD) signal only when internal address signal 104 and delayed internal address signal 116 have different logic states. ATD signal 140 thus signals a transition of address bit zero.
Address bit N and all intervening address bits between address bit zero and address bit N are treated similarly. External address signal 108 is input to buffer 110 to produce internal address signal 112. Internal address signal 112 is transmitted along address path 153 and also to delay circuit 128. The output of delay circuit 128 is input as delayed address signal 130 to XOR gate 126. XOR gate 126 also receives internal address signal 112 and outputs ATD signal 142 associated with address bit N. All ATD signals, one for each address bit input to integrated circuit 141, are input to OR gate 120. Therefore, when any of the ATD signals 0-N are active, ATD signal 144 will go active. An active ATD signal 144 activates master pulse generator 122 which outputs master pulse 124. Master pulse 124 is used to activate circuitry that prepares the memory for an access as previously described. When the device generating address bits A0-AN produces glitches on any one of the address lines, the circuit of FIG. 1 may cause improper operation of master pulse generator 122, and consequently, access errors in memory device 141. A glitch is a transition (low to high or high to low) of an input signal that crosses the trip point of the circuit receiving it, followed a short time later by a transition in the opposite direction that recrosses the trip point of the circuit.
FIG. 2 is a timing diagram showing proper operation of the circuit of FIG. 1 when an incoming address signal is glitchless. FIG. 2 shows voltage as a function of time for address signal 202, which is an internal address signal such as address signal 104. ATD signal 204 is a signal such as ATD signal 140. OR output 206 is the output of an OR gate such as signal 144. Master pulse 208 is the output of a master pulse generator such as master pulse generator 122. Data out 210 is the output of a memory device such as memory device 141. Address signal 202 is shown transitioning, where the transition of address signal 202 causes a pulse on ATD signal 204. The high going edge of ATD signal 204 causes a pulse on OR output 206, which in turn causes a master pulse 208 to be generated. The high going edge of master pulse 208 initiates sense amplifiers of the memory device. The result of a sensing operation by the sense amplifiers is latched by the low going edge of master pulse 208. In proper operation, the sense amplifiers have completed sensing and, therefore, valid data is latched by master pulse 210.
FIG. 3 is a timing diagram showing improper operation of a circuit such as that shown in FIG. 1. Similarly named signals have similar descriptions like those of their counterparts in FIG. 2. Here a pulse is generated in ATD signal 214 by a transition on address signal 212. The high going edge of ATD signal 214 causes a pulse on OR output 216, which in turn causes master pulse 218 to be generated as in FIG. 2. In FIG. 3, however, glitch 222 occurs in address signal 212. Glitch 222 propagates as shown in ATD signal 214 in OR output 216. Glitch 222 eventually causes generation of a second master pulse 218a. Because of the relationship between input pulse width to output pulse width for master pulse generator 122, master pulse 218a is too short, causing invalid data to be latched on the falling edge of master pulse 218a. Thus, the prior art address transition in detector circuit provides independent address paths and address transition detection paths and fails to account for potentially error-causing glitches on incoming address signals.